The present invention generally relates to dielectric/metal film stacks, and more specifically relates to eliminating IMC cracking in post wirebonded dies.
It has been observed that some post wire bonded dies that have undergone Cu/Low-K metallization show signature of ‘open’ fails after several hours of HTS (high temperature storage). Failure analysis on such parts shows cracks at the interface of intermetallic compound (IMC) and gold bond. FIG. 1 shows an X-SEM of a bonded die with IMC cracking.
Historically, IMC cracking in Au—Al wirebonds have been attributed to several causes including contamination on the surface of the Al-pads, incompatible film properties of the Al-films, presence of halides in the molding compounds, excessive levels of voids in the molding compounds and poorly optimized bonding and molding conditions. However, in the case of wire bond devices with Cu/Low-k metallization, the cracking of IMC persists despite careful control of the above-mentioned factors. Through a cumulative set of deductive experiments and use advanced analytical techniques, it has been determined that the cracking of IMC wire bond devices with Cu/Low-k metallization is a strong function of the tensile stresses in the film. It has been found that the unusually high tensile stresses generated in the Cu/Low-K stacks can drive excessive diffusion of Al into the Au bonds leading to very thick and Al-rich IMC phases. The unstable Al-rich phases eventually undergo reverse phase transformations to Au-rich phases; the associated volume change (very large˜30%) in such phase transformations can result in voiding and eventual cracking of the IMC. The way to prevent this issue then is to tailor the stresses in the Cu/Low-K stacks so that the Al-diffusion rates are controlled to a low enough level that the stable Au-rich phases are formed preferably when compared to Al-rich phases. This will prevent any tendencies for phase transformation in the system.
Stress Build-Up:
The present invention addresses the stress related issues that cause the IMC cracking and methods to eliminate the IMC cracking by controlling the macro stresses in the wafer. During Cu/Low-k processing, it has been found that there is cumulative stress buildup in wafers due to intrinsic stresses in metal and dielectric films and due to various thermal cycles. Thermal stresses are generated due to a mismatch between the temperature coefficients of expansion between metal, dielectric films and substrate, as illustrated in the following table:
Coefficient of thermal expansion for various filmMaterial(per degree Celsius)Al2.2E−05Cu1.7E−05Ti/TiN9.0E−06Ta/TaN6.0E−06Si3.0E−06SiO25.5E−07
Intrinsic stresses are generated during deposition. The stress state can be evaluated with freestanding films (or films on flexible substrates). Some general observations regarding stresses in thin films is provided below for reference:                1. Tensile: typically, an upward curve is generated due to repulsive forces between tapered grains in zone 1 structure formed by evaporation or sputtering with high pressure and low power.        2. Compressive: typically, a downward curve is generated due to atomic peening of crystal grains by reflected neutrals during sputtering.        3. Metals with Body Centered Cubic (BCC) structure, e.g., W, Ta (mostly refractory metals), can have extremely high compressive stress due to open lattice that allows atoms to be easily displaced.        4. Metals with Face Centered Cubic (FCC) structure, e.g., Cu, Al and Au (most noble metals), have very little intrinsic stress (low re-crystallization temperature).        5. Dielectric (CVD) films can be tensile or compressive depending on deposition parameters, e.g., temperature and plasma power.        
The macro stresses in the wafer can be measured by measuring the bow in the wafer and translating the values to stresses through Poisson's equations. In general, a positive wafer gap during the wafer bow measurement indicates tensile stresses in the wafers and a negative wafer gap indicates compressive stresses. FIG. 2 shows a normalized graph with stress accumulated on a wafer at various stages in the BEOL Cu/Low-k wafer processing.
It is evident from FIG. 2 that the tensile stresses on the wafer keep increasing in the wafer as more and more metallization steps are added to the film and the wafer experiences maximum tensile stress during deposition of the Aluminum pad. Aluminum and copper are known to contribute to tensile stresses, while the dielectric films can contribute to tensile or compressive stresses based on deposition conditions like temperature, time, etc. As the tensile stresses in the wafer build-up, the wafer can bow due to the warpage or macro stress distributions from the center to the edge of the wafer. However, the local stress distribution in the Aluminum pads is harder to characterize.